1. Field of the Invention
The present invention relates to bumping process, and in particular, to a bumping process to fabricate bumps with the higher height which enhances connection reliability between chips and a carrier by way of a single exposure to form stair-shaped openings in the photoresist layer.
2. Description of the Related Art
In the modern world with abundant information, the market of multi-media application is thus continuously growing. The development of Integrated Circuits (IC) packaging technology should be in line with the development of electronic devices, including digitization, network development, local area connections and user friendliness of electronic devices. To meet the above requirements, capacities of high-speed processing, multi-function, miniaturization, lightweight and low cost for the electronic devices have to be improved.
Thus, IC package technology has been developed toward the purposes of small-scale and high density. Ball Grid Array (BGA) packages, Chip-Scale Package (CSP), Flip Chip (F/C) packages and Multi-Chip Module (MCM) packages are hence developed. The density of the IC package refers to the number of pins per unit area. In view of the high density IC package, reducing the length of wires improves signal transmission speed, and therefore, the application of bumps becomes the main stream of high-density package.
FIGS. 1A to 1F are schematic cross-sectional views of steps for a conventional bumping process. Referring to FIG. 1A, a wafer 100 is first provided. A plurality of bonding pads 102 is formed on an active surface of the wafer 100. In addition, a passivation layer 106 is formed on the wafer 100, and the passivation layer 106 covers the active surface of the wafer 100 but exposes the bonding pads 102. Moreover, an under bump metallurgy (UMB) layer 104 is formed on the wafer 100, wherein the UBM layer 104 is disposed on the exposed surface of the bonding pads 102 and a portion of the passivation layer 106 around the bonding pads 102.
As shown in FIG. 1B, a photoresist layer 108 is formed on the active surface of the wafer 100. Thereafter, as shown in FIG. 1C, a plurality of openings 108a are formed in the photoresist layer 108 directly above the bonding pads 102 after photolithography and development. Through the openings 108a, a portion of the under-bump metallurgy (UBM) layer 104 is exposed.
As shown in FIG. 1D, a solder material is filled into the openings 108a by stencil printing so that a plurality of solder posts 110 is formed over the UBM layer 104. Thereafter, as shown in FIG. 1E, the photoresist layer 108 is removed to expose the solder posts 110.
Finally, as shown in FIG. 1F, a reflow process is then performed. During the reflow process, since the solder posts 110 are in a partially melted state, spherical-like solder posts 110 are formed due to the cohesion thereof. Then, the spherical-like solder posts 110 are cooled and b a plurality of spherical bumps 110a is obtained on the UBM layer 104.
FIG. 2 schematically shows the assembly between a chip and a printed circuit board, after forming bumps on the chip by the conventional bumping process. Referring to FIG. 1F and FIG. 2, after the bumping process is performed on the wafer 100 to form the bumps, the wafer 100 is sawed to form a plurality of separated chips 100a. Next, referring to FIG. 2, the chip 100a is bonded to a carrier 150 by flip chip bonding. The chip 100a is electrically connected to contacts 152 of the carrier 150 via the bumps 110a. The carrier 150 is, for example, a package substrate or a printed circuit board. Besides, an underfill 140 is filled between the chip 100a and the carrier 150 so as to protect the exposed surfaces of the bumps 110a. 
It should be noted that during the heating process, the bumps are subjected to thermal strain resulted from the difference in coefficients of thermal expansion (CTE) for the carrier and the chip. When the shear stress exerted to the bumps exceeds the tolerance range, cracks will occur, which results in short between the chip and the carrier. Besides, due to the fact that the sidewalls of the opening in the photoresist layer are substantially perpendicular to the active surface of the wafer, the volume and the height of the bumps fabricated by the conventional bumping process are limited by the thickness of the photoresist layer. Thus, the bumps are easily damaged by the shear stress generated by thermal strain between the chip and the carrier, and the reliability of package is poor.
In order to overcome the above drawbacks, another conventional bumping process is proposed. FIGS. 3A to 3F are schematic sectional views of another conventional bumping process. Referring to FIG. 3A, a wafer 210 is first provided, and the wafer 210 has a plurality of bonding pads 214 thereon and a passivation layer 216 covering an active surface of the wafer 210. The passivation layer 216 exposes the bonding pads 214. Furthermore, an under bump metallurgy (UMB) layer 218 is formed over the wafer 210. The UBM layer 208 is disposed on the exposed surface of the bonding pads 214 and covering a portion area of the passivation layer 216 around the bonding pads 214.
A first patterned photoresist layer 220a is formed on the wafer 210 by a first photolithography process, and the first patterned photoresist layer 220a includes a plurality of first openings 222a exposing the surface of the UBM layer 218. Next, referring to FIGS. 3B and 3C, a second patterned photoresist layer 220b is formed over the wafer 210. Thereafter, a plurality of second openings 222b which expose the first opening 222a of the first patterned photoresist layer 220a, is formed in the second patterned photoresist layer 220b by a second photolithography process. Moreover, the size of the second openings 222b is larger than that of the first openings 222a. 
Referring to FIGS. 3D to 3F, a solder material is filled into the first opening 222a and the second opening 222b by, for example, stencil printing so as to form a plurality of solder posts 230 therein. Then, the first patterned photoresist layer 220a and the second patterned photoresist layer 220b are removed. Finally, a reflow process is performed to turn the solder posts 230 to spherical bumps 232.
In view of the above, the stair-shaped opening formed by the first and second patterned photoresist layers are fabricated via two separate photolithography processes, and the objective of increasing the height of the bump can be achieved by stacking two photoresist layers. However, performing two photolithography processes is not economical because not only the complexity and costs of production are increased but also the fabrication time is extended.